Formal reliability analysis of combinational circuits using theorem proving

Reliability analysis of combinational circuits has become imperative these days due to the extensive usage of nanotechnologies in their fabrication. Traditionally, reliability analysis of combinational circuits is done using simulation or paper-and-pencil proof methods. But, these techniques do not ensure accurate results and thus may lead to disastrous consequences when dealing with safety-critical applications. In this paper, we mainly tackle the accuracy problem of these traditional reliability analysis approaches by presenting a formal reliability analysis framework based on higher-order-logic theorem proving. We present the higher-order-logic formalization of the notions of fault and reliability for combinational circuits and formally verify the von-Neumann fault models for most of the commonly used logic gates, such as, AND, NOT, OR, etc. This formal infrastructure is then used along with a computer program, written in C++, to automatically reason about the reliability of any combinational circuit within a higher-order-logic theorem prover (HOL). For illustration purposes, we utilize the proposed framework to analyze the reliability of a few benchmark combinational circuits.